The invention relates to an inter-integrated circuit (I2C) slave device and, in particular, to providing the I2C slave device with read/write access to a random access memory (RAM) device.
I2C is a serial computer bus protocol that is typically utilized to connect integrated circuits (e.g., peripherals) in an embedded system or motherboard through the use of two bi-directional pins (clock and data). I2C is a multi-master bus that allows multiple integrated circuits to be connected to the same bus with each one having the ability to act as the I2C master device by initiating a data transfer. I2C slave devices are utilized in programmable logic devices (PLDs) for many applications such as I2C multiplexing and I2C based microprocessor control.
An I2C slave device contains registers than can be written to and read from by an I2C master device. When an I2C slave device is implemented in a PLD (e.g., a field programmable gate array “FPGA” and a complex programming logic device “CPLD”), each bit of an eight bit register consumes one logic element (e.g., in a FPGA) or one macrocell (e.g., in a CPLD) within the PLD. For example, a two hundred and fifty six register I2C slave would consume two thousand and forty eight logic elements (or macrocells), or about one third of the logic elements in a typical six thousand logic element device. The fewer logic elements consumed, the better, as the cost of a digital logic design is often measured as the ratio of the number of logic elements consumed per dollar cost of the device. As the required logic count of a design increases, the costs associated with the device will rise accordingly.